1. Field of the Invention
The present invention is directed to a voltage translation circuit for mixed voltage applications, and more particularly, to a voltage translation circuit that minimizes power dissipation thereof.
2. Discussion of the Prior Art
Advanced CMOS circuits use low operating voltages, such as 1.8 volts, while many other circuits operate at higher voltages, such as 3.6 volts (V). One of the key challenges for advanced CMOS designs is the ability to interface low voltage advanced CMOS circuits to circuits operating at higher voltages.
To operate devices having circuits that operate at different voltages, a voltage translation circuit is necessary to change one level of the operating voltage to another level. For example, a logic high level for CMOS 6X technology is 1.8V, while for other circuits, such as I/O (input/output) interface circuits or circuits connected to I/Os of the CMOS 6X devices, a logic high level is 3.6V. The higher 3.6V level, instead of the lower 1.8V level, may also be required for analog circuits connected to the CMOS 6X devices.
FIG. 1 shows a conventional voltage translation circuit 100 having a level converter circuit 105 and an I/O interface circuit 110. The level converter 105 changes the level of a signal, for example, from a signal ranging from 0 to 1.8V and its complement applied to nodes S2 and S3, respectively, to a signal ranging from 1.8 to 3.6V provided on node S1.
The I/O interface circuit 110 receives the signal ranging from 1.8 to 3.6V provided on node S1, and another signal ranging from 0 to 1.8V applied to node S4, and provides an output signal to an I/O pad 115 ranging from 3.6 to 0V. The I/O pad 115 is connected to other circuits (not shown) that are configured to operate with signals ranging from 0 to 3.6V instead of signals ranging from 0 to 1.8V. Thus, the conventional voltage translation circuit 100 allows a device to have circuits that operate with signals ranging from 0V to 1.8V, 1.8V to 3.6V, and 0V to 3.6V.
As shown in FIG. 1, the conventional level converter circuit 105 includes a first stack 120 of four CMOS transistors and a second stack 125 of two CMOS transistors. The first stack 120 has two PMOS transistors TP1 and TP2 and two NMOS transistors TN1 and TN2. Herein, a PMOS transistor is designated by a circle at its gate, and has a source located above the gate and a drain located below the gate. In comparison, the locations of the source and drain of an NMOS transistor are reverse that of the PMOS transistor. That is, the NMOS transistor has its drain located above the gate and a source located below the gate.
The first PMOS transistor TP1 has its source connected to a DC (direct current) voltage of OVdd, e.g., 3.6 VDC, and its drain connected to the source of the second PMOS transistor TP2. The gate of the first PMOS transistor TP1 is pulled up to Vdd, which is 1.8 VDC for example, while the gate of the second PMOS transistor TP2, designated as node S2, receives a signal ranging from 1.8V to 0V. This signal is the complement of a signal ranging from 0V to 1.8V applied to node S3, which is connected to the gate of the first NMOS transistor TN1. The source of the first NMOS transistor TN1 is connected to ground, while its drain is connected to the source of the second NMOS transistor TN2. The drains of the second NMOS and PMOS transistors TN2, TP2 are connected together.
The interconnected drain and source of the first and second PMOS transistors TP1, TP2 are connected to gates of PMOS and NMOS transistors of the second stack 125, designated as TP5 and TN5, respectively. Similar to source of the first PMOS transistor TP1 of the first stack 120, the source of the PMOS transistor TP5 of the second stack 125 is connected to the OVdd bus, pulling up this source to 3.6VDC, for example.
The source of the NMOS transistor TN5 of the second stack 125 is connected to the Vdd DC power source, providing 1.8VDC, for example. The drains of the NMOS and PMOS transistors TN5, TP5 of the second stack 125 are connected together.
The interconnected drain and source of the NMOS and PMOS transistor TN5, TP5 of the second stack 125 are connected to a gate of a PMOS transistor TP3 of a third stack 130, which gate is designated as node S1. The third stack 130 is part of the I/O interface circuit 110 and includes two PMOS transistors TP3, TP4 and two NMOS transistors TN3, TN4.
The source of the first I/O PMOS transistor TP3 is connected to the OVdd bus, while its drain is connected to the source of the second I/O PMOS transistor TP4. As with the source of the first NMOS transistor TN1 of the first stack 120, the source of the first I/O NMOS transistor TN3 is connected to ground. The gate of the first I/O NMOS transistor TN3, designated as node S4, receives a signal that varies from 0V to 1.8V, which is similar to the signal applied to node S3.
The drain of the first I/O NMOS transistor TN3 is connected to the source of the second I/O NMOS transistor TN2. The gates of the second I/O NMOS and PMOS transistors TN4, TP4 are pulled up to Vdd, which is 1.8VDC for example. The drains of the second I/O NMOS and PMOS transistors TN4, TP4 are connected together. The interconnected drains of the second I/O NMOS and PMOS transistors TN4, TP4, designated as node S5, are connected to the I/O pad 115 and provide a signal ranging from 3.6V to 0V.
The operation of the conventional voltage translation circuit 100 is now described. A signal and its complement that include pulses that have low and high voltage levels are applied at nodes S3 and S2, respectively. Illustratively, the low and high voltage levels are 0V and 1.8V, respectively.
When S3 is at 0V, and consequently S4 is at 1.8V, then the first NMOS transistor TN1 of the first stack 120 is turned OFF, as any CMOS transistor would be OFF when its gate and source are at the same voltage level. Because TN1 is OFF, no current flows through the path TP1-TP2-TN2-TN1 of the first stack 120.
The first PMOS transistor TP1 of the first stack 120 is ON because its gate is connected to Vdd of 1.8VDC, which is less than the voltage OVdd of 3.6Vdc applied to its source. As a result of TP1 being ON while TN1 being OFF, which prevents current flow down the first stack 120, the gates of transistors TP5 and TN5 of the second stack 125 are pulled up to 3.6V (OVdd) through the ON first PMOS transistor TP1 of the first stack 120.
The transistors TP5 and TN5 of the second stack 125 are configured as an inverter that output 3.6V (OVdd) and 1.8V (Vdd), when its input is 1.8V and 3.6V, respectively. Thus, the 3.6V level at the gates of transistors TP5, TN5 when S3=low is inverted to result in a voltage level of 1.8V at node S1 of the interconnected drains of transistors TP5, TN5. This 1.8V level at node S1 is the low state of the translated signal. In effect, the low state level of 0V at node S3, is translated to a new low state level of 1.8V at node S1, which is the output of the level converter circuit 105.
The voltage at node S1 is 1.8V when 3.6V is applied to the gates of the second stack transistors TP5, TN5 because the PMOS transistor TP5 is OFF and the NMOS transistor TN5 is ON. The PMOS transistor TP5 of the second stack 125 is OFF, since its source voltage OVdd of 3.6V is the same as its gate voltage. The NMOS transistor TN5 of the second stack 125 is ON, since its source voltage Vdd of 1.8V is the less than its gate voltage of 3.6V. Because the NMOS transistor TN5 is ON and the PMOS transistor TP5 is OFF, the voltage at node S1 is approximately the same as the voltage Vdd of 1.8V applied to the source of the ON NMOS transistor TN5.
When the true input of the level converter circuit 105 at node S3 changes from low to high, i.e., becomes 1.8V, and the complement input at node S2 becomes low, i.e., 0V, then the output at node S1 becomes high at 3.6V, as described below. When the voltage as S3 is high at 1.8V, TN1 turns ON since its gate voltage of 1.8V is larger than its source voltage of 0V. The ON first NMOS transistor TN1 switches ON the second NMOS transistor TN2 and draws current in the path TP1-TP2-TN2-TN1 of the first stack 120.
The second NMOS transistor TN2 limits the drain voltage of the first NMOS transistor TN1 to Vdd-Vt, where Vt is the threshold voltage of the NMOS transistors TN1, TN2, which is approximately equal to 0.3V. Thus, the voltage at the drain of TN1, which is connected to the source of TN2, is approximately 1.5V. The second NMOS transistor TN2 is ON because the voltage at its gate (1.8VDC) is higher than the voltage at its source, which is approximately 1.5V in this example.
Note, the first PMOS transistor TP1 of the first stack 120 is always ON, since its gate voltage of 1.8VDC (Vdd) is less than its source voltage of 3.6VDC (OVdd). When the true input node S3 is 1.8V, the voltage at the gate of the second PMOS transistor TP2 of the first stack 120, which is the complement input node S2, is 0V. This turns ON the second PMOS transistor TP2 because its gate is at a lower voltage than its source voltage.
The strengths of the first stack 120 of all four transistors TP1, TP2, TN1, TN2 are designed such that the voltage to the gates of transistors TP5, TN5 of the second stack 125 falls from 3.6V to 1.8V when the first stack input voltages of 0V, 1.8V on nodes S3, S2 respectively, change to 1.8V, 0V. The strength of each transistor is determined by its size, in particular, by the ratio of its channel width to length ratio (W/L).
The transistors TP5, TN5 of the second stack 125 invert the 1.8V level on their gates to OVdd of 3.6V as follows. The voltage at node S1 is 3.6V when 1.8V is applied to the gates of the second stack transistors TP5, TN5 because the PMOS transistor TP5 is ON and the NMOS transistor TN5 is OFF. The PMOS transistor TP5 of the second stack 125 is ON, since its source voltage OVdd of 3.6V is the greater than its gate voltage of 1.8V. The NMOS transistor TN5 of the second stack 125 is OFF, since its source voltage Vdd of 1.8V is the same as its gate voltage. Because the NMOS transistor TN5 is OFF and the PMOS transistor TP5 is ON, the voltage at node S1 is approximately the same as the voltage OVdd of 3.6V applied to the source of the ON PMOS transistor TP5.
The third stack 130 of the I/O interface circuit 110 operates in a manner similar to the first stack 120 of the level converter circuit 105. In particular, its output signal at the I/O output node S5, which is connected to the I/O pad 115, is high (3.6V) when the signal at node S1 is low (1.8V), and the signal at node S4 is low (0V). Similarly, when the signal at node S1, is high (3.6V), and the signal at node S4 is high (1.8V), then the output signal at the I/O output node S5 is low (0V), as follows.
The 1.8V level at node S1 turns ON the TP3 transistor, while the 0V level at node S4 turns OFF the TN3 transistor. Similar to the first stack 120, the OFF NMOS transistor TN3 prevents current flow down the third stack 130. Thus, the OVdd voltage level connected to the source of the ON TP3 transistor provides the high voltage level of 3.6V at node S5 which is connected to the input to the I/O pad 115. Note, the TP4 transistor is also ON since the voltage level of 1.8VDC is less than its source voltage level of 3.6V, which is provided through the ON TP3 transistor.
When the inputs of the third stack 130 at nodes S1, S4, go high, than the voltage at the output node S5 goes low to 0V as follows. The 3.6V level at node S1 turns OFF the TP3 transistor, because its source and gate are at the same voltage level. This also turns OFF the TP4 transistor. The 1.8V level at node S4 turns ON the TN3 transistor, which also turns ON the TN4 transistor, as described in connection with the first and second NMOS transistors of the first stack 120. This connects the node S5 to ground and pulls down the 3.6V level on node S5 to 0V.
In summary, the conventional voltage translation circuit 100 translates the 0V and 1.8V voltage levels of the input signal at node S2 (and its complement at node S3) to new voltage levels at node S5, namely, 3.6V and 0V.
The conventional voltage translation circuit 100 suffers from a number of drawbacks. One disadvantage of the conventional voltage translation circuit 100 is that the first stack 120 of the conventional level converter circuit 105 consumes large amounts of power. This is because current I continuously flows through the four transistors TP1, TP2, TN2, TN1 of the first stack 120 when node S3 is high (1.8V), resulting in unwanted power dissipation.
Furthermore, this unwanted DC power dissipation is directly proportional to a desired performance, such as speed, of the I/O of the conventional voltage translation circuit 100. For example, to achieve a higher desired speed, a larger undesired current flowing through the four transistors TP1, TP2, TN2, TN1 of the first stack 120 is required. Thus, there is a direct tradeoff between switching speed and DC power dissipation.
Another disadvantage is that the ratio of strengths of the four transistors TP1, TP2, TN2, TN1 of the first stack 120 is critical in order to guarantee that the voltage on the gates of transistors TP5, TP5 of the second stack 125 is within an acceptable range of Vdd, e.g., 1.8V, when S3 is high and current I is flowing down the first stack 120. That is, the four transistors TP1, TP2, TN2, TN1 of the first stack 120 must be properly fabricated to provide a desired voltage division, namely, to provide 1.8V at the gates of transistors TN5, TP5 of the second stack 125 when the voltage at node S3 is high and current I is flowing down the first stack 120. This requirement results in tighter manufacturing tolerances than otherwise necessary for the conventional level converter circuit 100 to function properly.